Fitting more Data-Driven Multithreading Cores into the Chip
نویسندگان
چکیده
In this paper we explore the potential of reducing the cache size of the cores in the DDM-CMP architecture and implementing additional on-chip processors in the space saved. With this technique we almost double the already high speedup the DDM-CMP architecture has compared to a state-of-the-art high-end single chip microprocessor. The proposed DDM-CMP scheme achieves speedup ranging from 5.2 to 14.9 compared to an equal hardware budget Pentium 4. Additionally, we analyze the potential a DDM-CMP architecture offers for improving the thermal characteristics of the chip thus extending life time and reducing power consumption.
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